The present invention relates to a multi-core LSI (multi-core data processor) on which a plurality of CPUs is mounted over the same LSI.
In a multi-core LSI over which the CPUs are mounted on the same LSI, when the CPUs are debugging software that runs independently of each another, if a shared bus has hung up because a program runs out of control (access to an unintended region etc.), it is not possible to identify which access by which CPU has caused the hang up and debugging of software becomes difficult to perform.
The case where a certain CPU runs out of control to cause a shared bus to hang up while other CPUs are running normally corresponds to the above case. In this case, due to the hang up of the shared bus, not only the CPU to be debugged but also other normal CPUs can no longer access and come to a stop. Consequently, it has been impossible to effectively debug software in a multi-core LSI even using a debug technique for a single-core LSI (LSI mounting one CPU).
As a technique for debugging in a single-core LSI, the following (1) and (2) are known.
(1) A system controller monitors a shared bus and if the access does not terminate after a predetermined time elapses (that is, a CPU runs out of control), the system controller detects it, outputs a pseudo response signal to the shared bus, and terminate the access by the CPU while accessing, and at the same time, causing the CPU to execute an interrupt processing. After that, the operation of the CPU is analyzed and which CPU has run out of control at which point in the program is identified by checking at which point in the program the interrupt processing has been processed (prior art 1).
(2) A WDT (Watch Dog Timer) is known as a function to detect a timeout for a fixed processing period of time among processing of software. In this case, at which point the CPU has run out of control is identified by detecting a timeout using a WDT and causing the CPU to execute an interrupt processing (prior art 2).
As a prior art document about the detection of timeout, patent document 1 (Japanese patent laid-open No. 2001-167067) is known.